The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
In a computing system, to access a solid-state drive (SSD), a host processor typically communicates with the SSD controller via a non-volatile memory host controller interface, which is usually adapted for a peripheral component interconnect express (PCIe) bus. The non-volatile memory host controller interface adopts a non-volatile memory express (NVMe) protocol, which defines communication between the host processor and a target device for accessing an non-volatile memory (NVM) sub-system. Conventionally, the host processor is directly connected with the NVM sub-system, e.g., a storage device, via a PCIe bus.